1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a structure of well regions provided in the surface of a semiconductor substrate.
2. Description of the Background Art
FIG. 53 is a sectional view showing a conventional semiconductor memory device having a peripheral circuit region and a memory cell region. Referring to FIG. 53, n type wells 103 and 105 are formed on the main surface of a p type semiconductor substrate 101 with a predetermined space. A p type MOS field effect transistor (hereinafter referred to as an "FET") is formed in a predetermined region on the main surface of n type well 103. The p type MOSFET is formed in a predetermined region on the main surface of n type well 105. On the other hand, an n type MOSFET is formed on the main surface of semiconductor substrate 101 between n type wells 103 and 105. The above described two p type MOSFETs and one n type MOSFET constitute the peripheral circuit region.
Further, the n type MOSFET is directly formed in a predetermined region on the main surface of semiconductor substrate 101 at a position separated from the peripheral circuit region by an element isolation insulating film 107. A trench type capacitor is formed so as to be connected to one source/drain region of the n type MOSFET. The n type MOSFET and the trench type capacitor constitute the memory cell region.
Semiconductor substrate 101 and n type wells 103 and 105 are provided with impurity regions 101a, 103a, and 105a for potential fixation, respectively.
Further, element isolation insulating films 109, 111, 113, 115, and 117 are formed in necessary regions on the main surface of semiconductor substrate 101.
It is preferable in general for a transistor not to have a backgate bias applied for higher speed operation. However, depending on where it is formed, it is sometimes better for a transistor such as one formed in a memory cell portion of a dynamic random access memory (hereinafter referred to as a "DRAM") to have a backgate bias applied in order to prevent a soft error and improve an element isolation breakdown voltage. Therefore, it is the most desirable to apply the most suitable backgate biases to respective transistors.
With regard to this, in the above described conventional semiconductor memory device shown in FIG. 53, the backgate biases of respective transistors 131, 133, and 135 are all fixed at the same value by a voltage of semiconductor substrate 101. Therefore, in the conventional semiconductor memory device, it is difficult to apply the most suitable backgate biases to respective transistors.
Further, in the conventional semiconductor memory device, such a problem as a latch up phenomenon and a soft error occurs with miniaturization of elements.
Further, the conventional semiconductor memory device also has a problem as to the characteristics of an input protecting circuit with increase of performance.
As described above, in the conventional semiconductor memory device, it is difficult to apply the most suitable backgate biases independently to respective transistors.
Although it is desired to apply a substrate potential (hereinafter referred to as a "VBB") generated by internal circuitry to the memory cell portion, application of VBB also to a complementary field effect transistor (hereinafter referred to as a "CMOSFET") portion causes generation of latch up.
In a bulk CMOS structure, a parasitic thyristor element is rendered conductive to cause a large current to flow between power supply terminals of the CMOS circuit, whereby the circuit operation is hampered and the IC in itself is destroyed. This phenomenon is generally called latch up. FIG. 54 shows a parasitic thyristor structure of a bulk CMOS IC having an n well structure. If a voltage lower than Vss is applied to an n.sup.+ drain 1302 in such a structure, for example and electrons are injected from n.sup.+ region 1302 to a p type substrate 1300, some of the electrons are collected in an n well 1303 (the collector of a lateral npn transistor Tnpn) to reach an n.sup.+ region 1304 through n well 1303. This current is to flow through a resistor 1305 of n well 1303 in FIG. 54. If this current is sufficiently large and a pn junction on the source side of a pMOS transistor is forward biased by a voltage drop caused by resistor 1305, a vertical pnp transistor 1306 is rendered conductive, causing a collector current generated by holes to flow in p type substrate 1300. If this current is large enough to cause a pn junction on the source side of an nMOS transistor to be forward biased by a voltage drop caused by a resistor 1309, a lateral npn transistor is now rendered conductive. Such a collector current renders pnp transistor 1306 conductive more strongly. With a positive feedback formed as described above, a large current remains supplied between Vcc and Vss independent of the current from the n.sup.+ drain which served as an initial trigger. In order to exit from this state, it is necessary to cut a current (holding current) per se which flows in the parasitic thyristor. Since the characteristics of the parasitic thyristor tend to be improved as miniaturization of the CMOS IC, the latch up is a serious problem in higher integration of the CMOS IC.
More specifically, when substrate potential VBB generated by the internal circuitry is applied to the CMOSFET portion, VBB abruptly changes in rising of power supply potential Vcc at the time of power-on, as shown in FIG. 55. At this time, the latch up sometimes occurs.
A portion related to the CMOS circuit has a parasitic thyristor structure by mixture of p channel transistor regions and n channel transistor regions. Therefore, a so-called latch up phenomenon occurs as described above. In particular, when not a potential having a strong supplying capability such as an externally applied ground potential but substrate potential VBB generated by the internal circuitry is applied, change of VBB often causes generation of the latch up. More specifically, when substrate potential VBB generated by the internal circuity has not been decided yet at the time of power-on, the potential of a power supply line node abruptly rises in response to power-on. Through the coupling capacitance between the power supply line node and the substrate, the substrate potential increases. As a result, when the substrate potential attains a positive value, a junction between the p type substrate and the n type source/drain region is forward biased, causing the latch up.
Other than the latch up, the conventional semiconductor memory device suffers from generation of a soft error which becomes conspicuous as miniaturization of the elements, complication of the element isolation structure, and low performance of the input protecting circuit as improvement of the semiconductor memory device in performance.